Flat cathode ray tube (CRT) displays include displays which exhibit an large aspect ratio (e.g., 10:1 or greater) with respect to conventional deflected-beam CRT displays, and which display an image in response to electrons striking a light emissive material. The aspect ratio is defined as the diagonal length of the display surface to the display thickness. The electrons which strike the light emissive material can be generated by various devices, such as by field emitter cathodes or thermionic cathodes. As used herein, flat CRT displays are referred to as flat panel displays.
Conventional flat panel displays typically include a faceplate structure and a backplate structure which are joined by connecting walls around the periphery of the faceplate and backplate structures. The resulting enclosure is usually held at a vacuum pressure. To prevent collapse of the flat panel display under the vacuum pressure, a plurality of electrically resistive spacers are typically located between the faceplate and backplate structures at a centrally located active region of the flat panel display.
The faceplate structure includes an insulating faceplate (typically glass) and a light emitting structure formed on an interior surface of the insulating faceplate. The light emitting structure includes light emissive materials, or phosphors, which define the active region of the display. The backplate structure includes an insulating backplate and an electron emitting structure located on an interior surface of the backplate. The electron emitting structure includes a plurality of electron-emitting elements (e.g., field emitters) which are selectively excited to release electrons. The light emitting structure is held at a relatively high positive voltage (e.g., 5 kV) with respect to the electron emitting structure. As a result, the electrons released by the electron-emitting elements are accelerated toward the phosphor of the light emitting structure, causing the phosphor to emit light which is seen by a viewer at the exterior surface of the faceplate (the "viewing surface").
FIG. 1 is a schematic representation of the viewing surface of a flat panel display 100. The faceplate structure 20 of flat panel display 100 includes a light emitting structure which is arranged in a plurality of rows of light emitting elements (i.e., pixel rows), such as pixel rows 1-10. Flat panel display 100 typically includes hundreds of pixel rows, with each row typically including hundreds of pixels. Spacers 101-104 extend horizontally across display 100 in parallel with pixel rows 1-10. Pixel rows 1-10 and spacers 101-104 are greatly enlarged in FIG. 1 for purposes of illustration.
The electron emitting structure of flat panel display 100 is arranged in rows of electron emitting elements which correspond with the pixel rows of faceplate structure 20. All of the electron emitting elements in a given row are simultaneously activated (i.e., fired). In an activated row of electron emitting elements, any electron emitting elements corresponding to pixels that are to be black are, of course, not actually activated even though the row of electron emitting elements is generally described as being activated. With this in mind, the activation of a row of electron emitting elements (or a pixel row) more precisely means that the row is selected to participate in information display. The rows of electron emitting elements are sequentially activated. Thus, the row of electron emitting elements corresponding to pixel row 1 is activated first, followed by the sequential activation of the rows of electron emitting elements corresponding to pixel rows 2-10. The firing order continues in the direction illustrated by arrow 110.
FIG. 2 is a cross sectional view of flat panel display 100 along section line 2--2 of FIG. 1. FIG. 2 illustrates faceplate structure 20, which includes faceplate 21 and light emitting structure 22, backplate structure 30, which includes backplate 31 and electron emitting structure 32, and spacer 101. Light emitting structure 22 includes pixel rows 1-10, and electron emitting structure 32 includes corresponding rows of electron emitting elements 1a-10a.
As previously described, the rows of electron emitting elements 1a-10a are sequentially fired at corresponding pixel rows 1-10. When the electrons emitted from the electron emitting elements 1a-10a strike the light emitting material of pixel rows 1-10, electron scattering occurs. As illustrated for pixel rows 6-9, the scattered electrons can strike spacer 101. The energy of the scattered electrons which strike spacer 101 can be sufficient to free electrons from spacer 101, thereby positively charging the surface of spacer 101. Spacer 101 is rapidly charged as the rows of electron emitting elements approaching spacer 101 are sequentially activated.
When the row (or rows) of electron emitting elements which are located immediately adjacent to spacer 101 (e.g., electron emitting element 10a) are activated, the positive charge which has built up on spacer 101 can be sufficient to deflect the emitted electrons toward spacer 101. As a result, the pixel rows immediately adjacent to spacer 101 (e.g., pixel row 10) may only receive a fraction of the electrons emitted from their corresponding rows of electron emitting elements, thereby causing these pixel rows to appear dark. Even slight deflection of the emitted electrons can result in perceivable pixel distortion adjacent to spacer 101. That is, electrons emitted from electron emitting element 10a can be deflected and strike pixel row 10 at a position which is off-center within pixel row 10, thereby causing distortion in pixel row 10. For these reasons, the viewer may perceive distorted (e.g., dark or light) pixel lines adjacent to spacer 101.
Prior art spacers have included electrically resistive coatings which help to bleed off the charge which is built up on the spacer surfaces. However, such resistive coatings, by themselves, can be insufficient to reduce the charging of the spacer surfaces to an acceptable level.
It would therefore be desirable to have methods and/or structures which reduce the charging of the spacer surfaces to an acceptable level during operation of flat panel display 100.